This invention relates to etching methods used in the fabrication of integrated electronic circuits on a semiconductor substrate such as silicon, particularly a single-chamber (in situ) method of anisotropically plasma etching a sandwich structure of a silicon oxide over polycrystalline silicon over a gate oxide.
An electronic circuit is chemically and physically integrated into a substrate such as a silicon wafer by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication, or insulative, for insulator and capacitor fabrication. They can also be of differing conductivity types, which is essential for transistor and diode fabrication. Degrees of resistance, capacitance, and conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible. Fabrication can be quite complex and time consuming, and therefore expensive. It is thus a continuing quest of those in the semiconductor fabrication business to reduce fabrication times and costs of such devices in order to increase profits. Any simplified processing step or combination of processes at a single location becomes a competitive advantage.
A common requirement in integrated circuit (IC) fabrication is the etching of a "sandwich" structure such as shown in FIG. 1A, having a layer of silicon dioxide ("oxide") over a layer of polycrystalline silicon ("poly") over a layer of thin oxide (often called "gate oxide", because of its frequent use in transistor gates). Oxide is an insulator with dielectric properties. Poly is resistive in nature, but is made less resistive when doped with an element having less or more than 4 valence electrons, such as phosphorus.
Two basic types of etch techniques can be used: chemical or "wet", and plasma or "dry". Etch chemistries for oxide and for poly are well known. Ordinarily, a mask layer is first deposited on a layer to be etched, and a mask opening made in the mask layer by photolithographic means, exposing a portion of the layer to be etched. An appropriate etch technique and chemistry is employed, which acts only on the exposed portion.
Difficulties may arise when more than one layer is desired etched at a single site because of different requirements for each: an etch chemistry for the bottom layer may interfere with a layer already etched through and exposed along the sidewall. Often these difficulties require changes between wet and dry techniques, and different types of etchers.
It is desirable to etch multiple layers at a single processing site. Less handling of the IC is required, which reduces handling errors. Less masking steps may also be required, which directly reduces fabrication costs.
Both oxide and poly can be etched in a single parallel plate plasma reactor chamber. However, an oxide is typically etched in fluorine deficient fluorocarbon based plasmas, whereas poly is often etched in fluorine or chlorine based plasmas. Reactor electrode materials may also differ: for oxide etch, an erodible electrode such as graphite or silicon is often used to provide a source of carbon or silicon for etch selectivity, whereas for poly etch, a non-erodible electrode is preferred.
If a single-chamber process were attempted using conventional art to etch an oxide/poly sandwich structure, the erodible electrode required for oxide etch would be destroyed by the poly etchants. Using conventional methods, the two steps are not profitably compatible.
It is desirable to etch an oxide/poly/oxide sandwich such as shown in FIG. 1A, "in situ", that is, performing all required steps within a single etch chamber, using a common electrode.